FIG. 6 illustrates a configuration example of a front end unit of a reception circuit of a serializer/de-serializer (SerDes). FIG. 6 illustrates an example of an NRZ (Non Return to Zero) reception circuit which receives a binary NRZ signal of “0” or “1”. In the reception circuit illustrated in FIG. 6, an amplifier 601 amplifies a binary NRZ signal SIN inputted to a serial signal input terminal, and comparators 602-L0 and 602-L1 which a comparator circuit 602L includes and comparators 602-H0 and 602-H1 which a comparator circuit 602H includes each perform determination of “0” and “1” and output a determination result.
In FIG. 6, an example of a half-rate configuration in which data is sampled in a half cycle of a data rate by the comparators 602-L0, 602-L1, 602-H0, and 602-H1 is illustrated. Further, an example of a configuration in which boundary detection related to the binary NRZ signal is performed by comparators 602-C0 and 602-C1 which a comparator circuit 602C includes and a clock data recovery circuit operates with a phase comparator by 2× sampling is illustrated. Therefore, as illustrated in FIG. 6, four-phase clocks I, Q, IX, and QX corresponding to phases of 0 degrees, 90 degrees, 180 degrees, and 270 degrees respectively are supplied. Operation timings of the comparators 602-L0, 602-L1, 602-H0, and 602-H1 which determine data of the binary NRZ signal are controlled based on the clocks I and IX, and operation timings of the comparators 602-C0 and 602-C1 which perform edge determination of data for phase detection of clock data recovery are controlled based on the clocks Q and QX.
In the example illustrated in FIG. 6, in order to remove an effect due to inter symbol interference (ISI) of data which occurs in a transmission path and heighten reception accuracy, a decision feedback equalizer (DFE) which compensates a signal loss due to the inter symbol interference based on a determination result of past data is applied. In FIG. 6, in order to compensate the effect due to the inter symbol interference after 1 unit interval (UI), a one-tap DFE which compensates the signal loss due to the inter symbol interference based on data before 1 UI is applied.
In FIG. 6, a determination level of the comparators 602-L0 and 602-L1 which the comparator circuit 602L includes and a determination level of the comparators 602-H0 and 602-H1 which the comparator circuit 602H includes are deviated, and based on a previous determination result which is before 1 UI, a determination result of the comparator which is to be selected is selected by selectors 603 and 604 provided in a subsequent stage of the comparators. The selected data is used for selection determination of data after next 1 UI.
For example, determination results of the comparator 602-L0 and the comparator 602-H0 are inputted to the selector 603. When output data of the selector 604 which is a determination result before 1 UI is “0”, the selector 603 selects the determination result of the comparator 602-L0, which is outputted as output data, and when the output data of the selector 604 is “1”, the selector 603 selects the determination result of the comparator 602-H0, which is outputted as output data. Further, for example, determination results of the comparator 602-L1 and the comparator 602-H1 are inputted to the selector 604. When output data of the selector 603 which is a determination result before 1 UI is “0”, the selector 604 selects the determination result of the comparator 602-L1, which is outputted as output data, and when the output data of the selector 603 is “1”, the selector 604 selects the determination result of the comparator 602-H1, which is outputted as output data.
Data is sampled alternately in the reception circuit with the half-rate configuration in this manner, thereby resulting in a determination result of a comparator in which data before 1 UI is operated in a phase opposite to a target comparator and allowing the reception circuit of the one-tap DFE to be configured by a simple configuration as illustrated in FIG. 6. A timing aligner 605 synchronizes data to be inputted at a timing corresponding to each of the four-phase clocks I, Q, IX, and QX and different from one another with a single clock and outputs the data. This makes it possible that a not-illustrated demultiplexer in a subsequent stage performs data processing in the single clock.
FIG. 7 illustrates another configuration example of a front end unit of a reception circuit of a serializer/de-serializer. FIG. 7 illustrates an example of a pulse amplitude modulation 4 (PAM4) reception circuit which receives not the binary NRZ signal but a 4-valued pulse amplitude modulation signal referred to as PAM4. In the PAM4 reception circuit illustrated in FIG. 7, an amplifier 701 amplifies a 4-valued PAM4 signal SIN inputted to a serial signal input terminal, and comparators 702-L0 and 702-L1 which a comparator circuit 702L includes, comparators 702-Z0 and 702-Z1 which a comparator circuit 702Z includes, and comparators 702-H0 and 702-H1 which a comparator circuit 702H includes determine data at three determination levels, thereby determining an input signal as a 3-bit thermometer code. Thermometer codes to be obtained, of “000”, “001”, “011”, and “111” correspond to four values of 0, 1, 2, and 3 respectively, and a logic circuit (PAM4 decoder) 704 to which the thermometer codes are inputted via a timing aligner 703 performs this conversion.
Also in FIG. 7, an example of a configuration in which data is sampled in a half cycle of a data rate is illustrated. Further, an example of a configuration in which boundary detection related to the 4-valued PAM4 signal is performed by comparators 702-C0 and 702-C1 which a comparator circuit 702C includes and a clock data recovery circuit operates with a phase comparator by 2× sampling is illustrated. Operation timings of the comparators 702-L0, 702-L1, 702-Z0, 702-Z1, 702-H0, and 702-H1 which determine data of the 4-valued PAM4 signal are controlled based on the clocks I and IX, and operation timings of comparators 702-C0 and 702-C1 which perform boundary detection for phase detection of clock data recovery are controlled based on clocks Q and QX.
There has been proposed a clock data recovery (CDR) circuit which has both functions of a CDR circuit of a phase locked loop method and a CDR circuit of an over-sampling method and allows switching between both the methods (refer to Patent Document 1). There has been proposed a communication semiconductor integrated circuit in which a ΔΣ (sigma-delta) type analog-digital conversion circuit capable of changing the number of operating comparators among comparators configuring a quantizer according to a communication system, and obtaining a desired noise shape characteristic while corresponding to two communication systems is built (refer to Patent Document 2).    Patent Document 1: Japanese Laid-open Patent Publication No. 2014-60583    Patent Document 2: Japanese Laid-open Patent Publication No. 2006-254261
A PAM4 signal is capable of communicating data of two bits in one symbol, and therefore it is possible to achieve a double data rate in the PAM4 signal compared with an NRZ signal, but on the other hand, the NRZ signal is excellent in reception accuracy due to a large eye opening compared with the PAM4 signal. It is preferable that communication can be performed by selecting an appropriate modulation method according to a communication situation such as a transmission line and a size of crosstalk in order to take advantage of the features of the respective signals, but when circuits corresponding to the respective modulation methods are each provided, a circuit scale becomes large.